Valentin Touzeau Homepage

Presentation

Since November 2019, I am a postdoc at the Real-Time and Embedded Systems Lab in Saarland University. Previously, I was PhD student at Verimag in Grenoble, under the supervision of David Monniaux and Claire Maïza.

Research interests

I am interested in software verification and security. My current research focuses in developping methods to detect Spectre attacks in softwares. Before that, I was working on designing efficient hardware cache analyses.

PhD Thesis

I defended my thesis, entitled "Static Analysis of Least Recently Used Caches: Complexity, Optimal Analysis, and Applications to Worst-Case Execution Time and Security" on October 8, 2019. The manuscript and the slides of my defense are available.

Publications

Here is a list of the research papers I contributed to. If you do not find the one you are looking for, you might find it on HAL or arXiv.

• JACM 2019: On the Complexity of Cache Analysis for Different Replacement Policies
• POPL 2019: Fast and exact analysis for LRU caches
• CAV 2017: Ascertaining Uncertainty for Efficient Exact Cache Analysis
• JWRTC 2016: Model Checking of Cache for WCET Analysis Refinement

Tools